rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADP3300 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 high accuracy anycap?* 50 ma low dropout linear regulator functional block diagram q2 thermal protection gm q1 cc bandgap ref driver r1 r2 ADP3300 out in err sd gnd features high accuracy (over line and load regulations at 25 8 c): 6 0.8% ultralow dropout voltage: 80 mv typical @ 50 ma requires only c o = 0.47 m f for stability anycap? = stable with all types of capacitors (including mlcc) current and thermal limiting low noise dropout detector low shutdown current: 1 m a 3.0 v to 12 v supply range C40 8 c to +85 8 c ambient temperature range several fixed voltage options ultrasmall sot-23 6-lead package excellent line and load regulations applications cellular telephones notebook, palmtop computers battery powered systems pcmcia regulators bar code scanners camcorders, cameras ADP3300-5 3 1 6 2 nr out in 4 r1 330k w e out c2 0.47 f v out = +5v on off gnd c1 0.47 f v in 5 figure 1. typical application circuit general description the ADP3300 is a member of the adp330x family of precision low dropout anycap? voltage regulators. the ADP3300 stands out from conventional ldos with a novel architecture and an enhanced process. its patented design requires only a 0.47 m f output capacitor for stability. this device is stable with any capacitor, regardless of its esr (equivalent series resistance) value, including ceramic types (mlcc) for space restricted appli- cations. the ADP3300 achieves exce ptional accu racy of 0.8% at room temperature and 1.4% overall accuracy over tempera- ture, line and load regulations. the dropout voltage of the ADP3300 is only 80 mv (typical) at 50 ma. the ADP3300 operates with a wide input voltage range from 3.0 v to 12 v and delivers a load current in excess of 50 ma. it features an error flag that signals when the device is about to lose regulation or when the short circuit or thermal overload protection is activated. other features include shutdown and optional noise reduction capabilities. the adp330x anycap? * anycap is a trademark of analog devices inc. ldo family offers a wide range of output voltages and output current levels from 50 ma to 300 ma: adp3301 (100 ma) adp3302 (100 ma, dual output) adp3304 (100 ma, dual output with separate grounds) adp3303 (200 ma) adp3306 (300 ma)
C2C rev. 0 ADP3300Cspecifications parameter symbol conditions min typ max units output voltage v out v in = nom v out +0.3 v to 12 v accuracy i l = 0.1 ma to 50 ma t a = +25 c C0.8 +0.8 % v in = nom v out +0.3 v to 12 v i l = 0.1 ma to 50 ma C1.4 +1.4 % line regulation d v o v in = nom v out +0.3 v to 12 v d v in t a = +25 c 0.02 mv/v load regulation d v o i l = 0.1 ma to 50 ma d i l t a = +25 c 0.06 mv/ma ground current i gnd i l = 50 ma 0.55 1.7 ma i l = 0.1 ma 0.19 0.3 ma ground current i gnd v in = 2.5 v in dropout i l = 0.1 ma 0.6 1.2 ma dropout voltage v drop v out = 98% of v o nominal i l = 50 ma 0.08 0.17 v i l = 10 ma 0.025 0.07 v i l = 1 ma 0.004 0.03 v shutdown threshold v thsd on 2.0 0.75 v off 0.75 0.3 v shutdown pin i sdin 0 < v sd 5 v 1 m a input current 5 < v sd 12 v @ v in = 12 v 22 m a ground current in i q v sd = 0, v in = 12 v shutdown mode t a = +25 c 0.005 1 m a v sd = 0, v in = 12 v t a = +85 c 0.01 3 m a output current in i osd t a = +25 c @ v in = 12 v 2 m a shutdown mode t a = +85 c @ v in = 12 v 4 m a error pin output leakage i el v eo = 5 v 13 m a error pin output low voltage v eol i sink = 400 m a 0.12 0.3 v peak load current i ldpk v in = nom v out + 1 v 100 ma output noise v noise f = 10 hzC100 khz @ 5 v output c nr = 0 100 m v rms c nr = 10 nf, c l = 10 m f30 m v rms note ambient temperature of +85 c corresponds to a typical junction temperature of +125 c under typical full load test conditions. specifications subject to change without notice. (@ t a = C40 8 c to +85 8 c, v in = 7 v, c in = 0.47 m f, c out = 0.47 m f, unless otherwise noted)
ADP3300 C3C rev. 0 other members of anycap? family 1 output package model current options 2 comments adp3301 100 ma so-8 high accuracy adp3302 100 ma so-8 dual output adp3304 100 ma so-8 dual output with separate grounds adp3303 200 ma so-8 high accuracy adp3306 300 ma so-8, tssop-14 high accuracy, high current notes 1 see individual data sheets for detailed ordering information. 2 so = small outline, tssop = thin shrink small outline. absolute maximum ratings* input supply voltage . . . . . . . . . . . . . . . . . . . . C0.3 v to +16 v shutdown input voltage . . . . . . . . . . . . . . . . . C0.3 v to +16 v error flag output voltage . . . . . . . . . . . . . . . . C0.3 v to +16 v noise bypass pin voltage . . . . . . . . . . . . . . . . . C0.3 v to +5 v power dissipation . . . . . . . . . . . . . . . . . . . . internally limited operating ambient temperature range . . . . C55 c to +125 c operating junction temperature range . . . . C55 c to +125 c q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 c q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c vapor phase (60 sec ) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. pin configuration 1 2 3 6 5 4 top view (not to scale) out nr gnd in err sd ADP3300 ordering guide model voltage output package option* ADP3300art-2.7 2.7 v sot-23 ADP3300art-3 3.0 v sot-23 ADP3300art-3.2 3.2 v sot-23 ADP3300art-3.3 3.3 v sot-23 ADP3300art-5 5.0 v sot-23 contact the factory for the availability of other output voltage options. *sot = surface mount. pin function descriptions pin mnemonic function 1 gnd ground pin. 2 nr noise reduction pin. used for further reduction of the output noise (see text for details). no connection if not used. 3 sd active low shutdown pin. connect to ground to disable the regulator output. when shutdown is not used, this pin should be connected to the input pin. 4 out output of the regulator, fixed 2.7, 3.0, 3.2, 3.3 or 5 volts output voltage. bypass to ground with a 0.47 m f or larger capacitor. 5 in regulator input. 6 err open collector output which goes low to indicate that the output is about to go out of regulation. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADP3300 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
output voltage ?volts output load ?ma 3.202 3.195 080 8 1624324048566472 3.201 3.200 3.199 3.198 3.197 3.196 v out = 3.2v v in = 7v figure 3. output voltage vs. load current temperature ? c output voltage ?% 0.2 ?.4 ?5 ?5 135 ? 15 35 75 95 115 55 0.1 0.0 ?.1 ?.2 ?.3 i l = 0 ?50ma figure 6. output voltage variation % vs. temperature input voltage ?volts 5 0 03 0 432 4 2 1 3 2 11 input/output voltage ?volts r l = 33 w v out = 3.2v r l = 64 w figure 9. power-up/power-down C4C rev. 0 input voltage ?volts output voltage ?volts 3.202 3.199 3.196 3.3 14 4 5 6 7 8 9 10 11 12 13 3.201 3.200 3.198 3.197 i l = 0ma i l = 10ma i l = 50ma v out = 3.2v figure 2. line regulation output voltage vs. supply voltage output load ?ma 820 ground current ?? 690 170 080 20 40 60 560 430 300 i l = 0 to 80ma v in = 7v figure 5. quiescent current vs. load current output load ?ma 120 96 080 20 40 60 72 48 24 0 input/output voltage ?mv figure 8. dropout voltage vs. output current \ input voltage ?volts 800 640 0 0 12.0 1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 480 320 ground current ? a 160 v out = 3.2v i l = 0ma figure 4. quiescent current vs. supply voltage temperature ? c 700 0 ?5 ?5 600 400 300 200 100 500 15 35 55 75 95 115 135 ? v in = 7v ground current ? a i l = 50ma i l = 0ma figure 7. quiescent current vs. temperature time ?? 0 0 100 200 2.0 v sd = v in c l = 0.47? r l = 66 w v out = 3.3v 1.0 3.0 4.0 5.0 6.0 7.0 8.0 20 input/output voltage ?volts 40 60 80 120 140 160 180 v in v out figure 10. power-up overshoot ADP3300Ctypical performance characteristics
ADP3300 C5C rev. 0 time ?? volts 3.220 3.180 0 200 20 40 60 80 100 120 140 160 180 3.210 3.200 7.5 7.0 3.190 r l = 64 w c l = 0.47? v out = 3.2v figure 12. line transient response time ?sec 200 0 05 1234 150 100 3.0 0 50 ma i out v out = 3.0v volts v out v in = 7v figure 15. short circuit current frequency ?hz ripple rejection ?db 0 ?00 10 100 10m 1k 10k 100k 1m ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 a. 0.47?, r l = 33k w b. 0.47?, r l = 64 w c. 4.7?, r l = 33k w d. 4.7?, r l = 64 w b d a c b d a c v out = 3.3v figure 18. power supply ripple rejection time ?? volts 3.220 3.180 0 200 20 40 60 80 100 120 140 160 180 3.210 3.200 7.5 7.0 3.190 r l = 3.2k w c l = 0.47? v in v out = 3.2v figure 11. line transient response time ?? volts 3.220 3.190 0 1000 200 400 600 800 3.205 3.200 50 1 3.195 v out = 3.2v c l = 4.7? ma i out = 50ma 1ma figure 14. load transient time ?? 2 0 0 100 20 40 60 80 1 0 4 3 3 v out = 3.2v r l = 64 w c l = 0.47? volts 3.2v v volts figure 17. turn off time ?? volts 3.220 3.190 0 1000 200 400 600 800 3.205 3.200 50 1 3.195 v out = 3.2v c l = 0.47? ma i out = 50ma 1ma figure 13. load transient time ? s 2 0 0 100 20 40 60 80 1 0 4 3 +3 v out = 3.2v r l = 64 w volts v out c l = 0.47? 3.2v c l = 4.7? v +3v figure 16. turn on frequency ?hz voltage noise spectral density ??/ hz 10 1 0.01 100 1k 100k 10k 0.1 0.47? bypass pin 5 to pin 1 v out = 3.3v, c l = 0.47?, i l = 1ma, c nr = 0 v out = 5v, c l = 0.47?, i l = 1ma, c nr = 0 v out = 2.7-5.0v, c l = 0.47?, i l = 1ma, c nr = 10nf v out = 2.7-5.0v, c l = 0.47?, i l = 1ma, c nr = 10nf figure 19. output noise density
ADP3300 C6C rev. 0 theory of operation the new anycap? ldo ADP3300 uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2 which is varied to provide the available output voltage option. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. gm ptat v os r4 r3 d1 r1 attenuation (v bandgap /v out ) r2 (a) compensation capacitor noninverting wideband driver q1 input c load output ADP3300 r load ptat current figure 20. functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input offset voltage that is repeatable and very well controlled. the temperature- proportional offset voltage is combined with the complimentary diode voltage to form a virtual bandgap voltage, implicit in the network, although it never appears explicitly in the circuit. ultimately, this patented design makes it possible to control the loop with only one amplifier. this technique also improves the noise characteristics of the amplifier by providing more flexibil- ity on the trade-off of noise sources that leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. although the r1, r2 resistor divider is loaded by the diode d1 and a second divider consist- ing of r3 and r4, the values are chosen to produce a tempera- ture stable output. this unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and esr of the load capacitance. most ldos place strict requirements on the range of esr values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resis- tance. moreover, the esr value, required to keep conventional ldos stable, changes depending on load and temperature. these esr limitations make designing with ldos more difficult because of their unclear specifications and extreme variations over temperature. this is no longer true with the ADP3300 anycap? ldo. it can be used with virtually any capacitor, with no constraint on the minimum esr. the innovative design allows the circuit to be stable with just a small 0.47 m f capacitor on the output. additional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. an impressive 1.4% accuracy is guaranteed over line, load and temperature. additional features of the circuit include current limit, thermal shutdown and noise reduction. compared to the standard solutions that give warning after the output has lost regula- tion, the ADP3300 provides improved system performance by enabling the err pin to give warning before the device loses regulation. as the chips temperature rises above 165 c, the circuit activates a soft thermal shutdown, indicated by a signal low on the err pin, to reduce the current to a safe level. to reduce the noise gain of the loop, the node of the main divider network (a) is made available at the noise reduction (nr) pin, which can be bypassed with a small capacitor (10 nfC100 nf). application information capacitor selection: anycap? output capacitors: as with any micropower device, output transient response is a function of the output capacitance. the ADP3300 is stable with a wide range of capacitor values, types and esr (anycap?). a capacitor as low as 0.47 m f is all that is needed for stability. however, larger capacitors can be used if high output current surges are anticipated. the ADP3300 is stable with extremely low esr capacitors (esr ? 0), such as multilayer ceramic capacitors (mlcc) or oscon. input bypass capacitor: an input bypass capacitor is not requ ired; however, for applications where the input source is high impedance or far from the input pins, a bypass capacitor is recommended. connecting a 0.47 m f capacitor from the input to ground reduces the circuits sensitivity to pc board layout. if a bigger output capacitor is used, the input capacitor should be 1 m f minimum. noise reduction a noise reduction capacitor (c nr ) can be used to further reduce the noise by 6 dbC10 db (figure 21). low leakage capacitors in the 10 nfC100 nf range provide the best performance. for load current less than 200 m a, a 4.7 m f output capacitor provides the lowest noise and the best overall performance. since the noise reduction pin (nr) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. the pad connected to this pin should be as small as possible. long pc board traces are not recommended.
ADP3300 C7C rev. 0 in out gnd ADP3300-5 nr + 6 1 2 3 4 5 on off + c2 4.7 f 330k w e out c1 1.0 f v out = +5v v in c nr 10nf figure 21. noise reduction circuit thermal overload protection the ADP3300 is protected against damage due to excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165 c. under extreme conditions (i.e., high ambient temperature and high power dissipation), where die temperature starts to rise above 165 c, the output current is reduced until die tempera- ture has dropped to a safe level. output current is restored when the die temperature is reduced. current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 125 c. calculating junction temperature device power dissipation is calculated as follows: pd = ( v in C v out ) i load + ( v in ) i gnd where i load and i gnd are load current and ground current, v in and v out are input and output voltages respectively. assuming i load = 50 ma, i gnd = 0.5 ma, v in = 8 v and v out = 3.3 v, device power dissipation is: pd = (8 C 3.3) 0.05 + 8 0.5 ma = 0.239 w d t = t j C t a = pd q j a = 0.239 165 = 39.4 c with a maximum junction temperature of 125 c, this yields a maximum ambient temperature of 85 c. printed circuit board layout consideration surface mount components rely on the conductive traces or pads to transfer heat away from the device. appropriate pc board layout techniques should be used to remove heat from the immediate vicinity of the package. the following general guidelines will be helpful when designing a board layout: 1. pc board traces with larger cross section areas will remove more heat. for optimum results, use pc boards with thicker copper and wider traces. 2. increase the surface area exposed to open air so heat can be removed by convection or forced air flow. 3. do not use solder mask or silkscreen on the heat dissipating traces because it will increase the junction to ambient thermal resistance of the package. shutdown mode applying a ttl high signal to the shutdown pin or tying it to the input pin will turn the output on. pulling the shutdown pin down to 0.3 v or below, or tying it to ground, will turn the output off. in shutdown mode, quiescent current is reduced to less than 1 m a. error flag dropout detector the ADP3300 will maintain its output voltage over a wide range of load, input voltage and temperature conditions. if the output is about to lose regulation, for example, by reducing the supply voltage below the combined regulated output and dropout voltages, the err pin will be activated. the err output is an open collector that will be driven low. once set, the err or flags hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load. application circuits crossover switch the circuit in figure 22 shows that two ADP3300s can be used to form a mixed supply voltage system. the output switches between two different levels selected by an external digital input. output voltages can be any combination of voltages from the ordering guide. ADP3300-5.0 out in gnd output select 5.0v 0v c1 1.0 f ADP3300-3.3 out in gnd c2 0.47 f v out = 5v/3.3v v in = 5.5v to 12v figure 22. crossover switch higher output current if higher current is needed, an appropriate pass transistor can be used, as in figure 23, to increase the output current to 1 a. v in = 6v to 8v v out = 5v @ 1a mje253* c2 10 f c1 47 f r1 50 w *aavid531002 heat sink is used in out gnd ADP3300-5 figure 23. high output current linear regulator constant dropout post regulator the circuit in figure 24 provides high precision with low dropout for any regulated output voltage. it significantly reduces the ripple from a switching regulator while providing a constant dropout voltage, which limits the power dissipation of the ldo to 15 mw. the adp3000 used in this circuit is a switching regulator in the step-up configuration.
ADP3300 C8C rev. 0 c3044CxxC7/97 printed in u.s.a. 6-lead surface mount package (sot-23) 0.122 (3.10) 0.106 (2.70) pin 1 0.071 (1.80) 0.059 (1.50) 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.020 (0.50) 0.010 (0.25) 0.059 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) outline dimensions dimensions shown in inches and (mm). d1 1n5817 c2 100? 10v l1 6.8 h r1 120 w ADP3300-5 in out gnd c3 2.2 f 5v @ 50ma c1 100 f 10v adp3000-adj i lim v in sw1 gnd sw2 fb v in = 2.5v to 3.5v r2 30.1k w 1% q1 2n3906 q2 2n3906 r4 274k w r3 124k w 1% figure 24. constant dropout post regulator
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